HDL Simulation - Revision history

Swinberg: Added Simulation category

2021-03-09T14:40:27Z

Added Simulation category

CRNKEE002: /* iVerilog */

2020-08-28T07:11:05Z

iVerilog

CRNKEE002: /* Available Simulators */

2020-08-20T10:39:10Z

Available Simulators

CRNKEE002: /* Verilog Testbench Directives */

2020-05-29T15:14:12Z

Verilog Testbench Directives

CRNKEE002: /* Testbenches in Verilog */

2020-05-29T15:08:35Z

Testbenches in Verilog

CRNKEE002: /* Testbenches in Verilog */

2020-05-29T15:07:41Z

Testbenches in Verilog

CRNKEE002 at 15:07, 29 May 2020

2020-05-29T15:07:26Z

CRNKEE002: /* Vivado */

2020-05-28T14:03:07Z

Vivado

CRNKEE002 at 11:20, 28 May 2020

2020-05-28T11:20:51Z

CRNKEE002: Created page with "Category: FPGAs Category: Software = Overview = When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet tim..."

2020-05-28T11:20:38Z

Created page with "Category: FPGAs Category: Software = Overview = When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet tim..."

New page

[[Category: FPGAs]]
[[Category: Software]]

= Overview =
When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet timing constraints (timing simulation). This page covers simulators that are used in the department, and, in some cases, instructions on how to use them. While there are of course many simulators, the ones below are used by academics, staff and researchers in the department.

= Vivado =
The Vivado Simulator comes as a part of the Vivado IDE. For details on the Vivado IDE, see [[Xilinx Vivado]].
For details specific to Vivado, you can find a video on simulation [https://www.youtube.com/watch?v=Cb5LRi5scMw here].
Simulate your design to ensure it operates as expected. You can run test benches to fully test your code.

Once you begin writing your modules you’re going to check that they’re working. You can do this through simulation.

Once you’ve synthesized your project, you should be able to click “run simulation”.

This will only run a simulation of your top module. It is far more useful to create a testbench.

<ol>
<li>Right click "Simulation Sources" and Select "Add new" <br>
In the dialog box, ensure Simulation sources is selected.
</li>

<li>Create it in a new simulation set, and use the checkbox to set it as active<br>
You can toggle which simulation source is active by setting it in the same way you'd set your top level module under design sources - just right click on the simulation source and select "Make active"
</li>

<li>Create a file for your testbench<br>
It's a good idea to name it the same as the module you're testing, followed by a "_tb" to distinguish it. For example, if you're creating a test bench for a clock, you might call the file "clock_tb". This file will appear under "non module sources" in the simulation set until you add some code to it.
</li>

<li>Add basic TB code to the modele<br>
A super simple testbench consists of a generated clock and an instantiation of the module you're testing. Add the simple clock generation code, save the file, and set it as top in the simulation source.
<pre>
module clock_tb();

//create a fake clock signal
reg clk = 0;

//toggle the clock
always begin
#1 clk = ~clk;
end

//

endmodule

</pre>
</li>

<li>You should now be able to instantiate modules and run behavioral simulations to ensure your design works. You can connect the modules in such a way to minic switches by setting register values and using delay constructs.
</li>

</ol>

@@ Line 48: / Line 48: @@
 The following is a collection of some HDL simulators used in the department.
 == iVerilog ==
 == EDAPlayground ==

@@ Line 47: / Line 47: @@
 = Available Simulators =
 The following is a collection of some HDL simulators used in the department.
 == Vivado ==
 The Vivado Simulator comes as a part of the Vivado IDE. For details on the Vivado IDE, see [[Xilinx Vivado]]. For details specific to Vivado, you can find a video on simulation [https://www.youtube.com/watch?v=Cb5LRi5scMw here].

← Older revision		Revision as of 15:14, 29 May 2020
Line 41:		Line 41:

	== Verilog Testbench Directives ==		== Verilog Testbench Directives ==
		+	Verilog directives allow you to do things which are not usually possible in hardware, only through simulation. This includes printing data to a screen, loading data from a text file, or stopping the simulation.
		+
		+	For a quick reference list of commands, see [http://www.techsystemsembedded.com/verilog_testbench.php this link].

	= Available Simulators =		= Available Simulators =

@@ Line 11: / Line 11: @@
 Testbenches in Verilog are simply modules that instantiate the DUT, control the inputs, and monitor the outputs accordingly. They usually contain a single DUT, an initial block to set starting conditions, and an always block to run the testbench. The general approach for a DUT is to use registers for inputs and wires for outputs. Of course there is much more to testbenches than that, but that is the short of it.
-For example, take a module that is meant to display switch values on LEDs:
+For example, take a module called ModuleToTest that is meant to display switch values on LEDs:
 <pre>
 module testbench();

@@ Line 38: / Line 38: @@
 </pre>
-=== Verilog Testbench Directives ==
+== Verilog Testbench Directives ==
 = Available Simulators =

@@ Line 1: / Line 1: @@
 [[Category: FPGAs]]
 [[Category: Software]]
 When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet timing constraints (timing simulation). This page covers some useful information on writing testbenches, as well simulators that are used in the department (and in some cases, instructions on how to use them). While there are of course many simulators, the ones below are used by academics, staff and researchers in the department.

@@ Line 2: / Line 2: @@
 [[Category: Software]]
-When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet timing constraints (timing simulation). This page covers simulators that are used in the department, and, in some cases, instructions on how to use them. While there are of course many simulators, the ones below are used by academics, staff and researchers in the department.
+When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet timing constraints (timing simulation). This page covers some useful information on writing testbenches, as well simulators that are used in the department (and in some cases, instructions on how to use them). While there are of course many simulators, the ones below are used by academics, staff and researchers in the department.
-Once you begin writing your modules you’re going to check that they’re working. You can do this through simulation.
+= Testbenches =
-Once you’ve synthesized your project, you should be able to click “run simulation”.
+= Testbenches in Verilog =
 This will only run a simulation of your top module. It is far more useful to create a testbench.
@@ Line 30: / Line 66: @@
 <li>Add basic TB code to the modele<br>
-A super simple testbench consists of a generated clock and an instantiation of the module you're testing. Add the simple clock generation code, save the file, and set it as top in the simulation source.
+A super simple testbench consists of a generated clock and an instantiation of the module you're testing. Add the simple clock generation code, save the file, and set it as top in the simulation source. See the example above.
 </li>

@@ Line 34: / Line 34: @@
 module clock_tb();
-//create a fake clock signal
+reg clk = 0; //create a fake clock signal
 //toggle the clock
@@ Line 41: / Line 40: @@
      #1 clk = ~clk;
 end
 endmodule
 </pre>
 </li>

← Older revision		Revision as of 11:20, 28 May 2020
Line 2:		Line 2:
	[[Category: Software]]		[[Category: Software]]

−	~~= Overview =~~
	When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet timing constraints (timing simulation). This page covers simulators that are used in the department, and, in some cases, instructions on how to use them. While there are of course many simulators, the ones below are used by academics, staff and researchers in the department.		When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet timing constraints (timing simulation). This page covers simulators that are used in the department, and, in some cases, instructions on how to use them. While there are of course many simulators, the ones below are used by academics, staff and researchers in the department.