Xilinx Vivado - Revision history

CRNKEE002: /* Simulate */

2020-05-28T11:49:35Z

Simulate

2020-05-28T10:54:42Z

Simulate

2020-05-12T08:01:54Z

Installation

2020-05-10T08:14:55Z

Simulate

2020-05-10T08:10:21Z

Creating a new project

2020-05-10T08:08:32Z

Installation

2020-05-04T13:05:59Z

Constraint Files

2020-05-04T13:05:38Z

Constraint Files

2020-04-22T15:58:58Z

Constraint Files

2020-04-22T15:53:17Z

Constraint Files

@@ Line 116: / Line 116: @@
 == Simulate ==
-There are multiple means for simulating HDL code. For an overview, visit [[HDL Simulation]].
+There are multiple means for simulating HDL code. For details, visit [[HDL Simulation]].
 == Implement ==

@@ Line 116: / Line 116: @@
 == Simulate ==
-You can find a video on simulation [here https://www.youtube.com/watch?v=Cb5LRi5scMw].
+There are multiple means for simulating HDL code. For an overview, visit [[HDL Simulation]].
 Simulate your design to ensure it operates as expected. You can run test benches to fully test your code.

@@ Line 9: / Line 9: @@
 Navigate to the file server on [http://hive.ee.uct.ac.za Hive] or go straight to the [https://www.xilinx.com/products/design-tools/vivado.html Vivado Download site], and scroll down to standalone installers. Grab the latest <strong>WebPack version</strong> of Vivado (See image). You may need to enter some details if using the Vivado site.
-A video on installation can be found [here https://www.youtube.com/watch?v=CQ-w-9qQD0s].
+A video on installation can be found [https://www.youtube.com/watch?v=CQ-w-9qQD0s here].
 [[File:Vivado-standalone.png|thumb]]

← Older revision		Revision as of 08:14, 10 May 2020
Line 116:		Line 116:

	== Simulate ==		== Simulate ==
		+	You can find a video on simulation [here https://www.youtube.com/watch?v=Cb5LRi5scMw].
	Simulate your design to ensure it operates as expected. You can run test benches to fully test your code.		Simulate your design to ensure it operates as expected. You can run test benches to fully test your code.

@@ Line 39: / Line 39: @@
 = Creating a new project =
 NB: If it's your first time running Vivado, it's suggested you install the board definitions first, as the IDE needs to be restarted to load new board definitions.
 To create a new project:
 # Select "Create Project" on the main page as Vivado Opens.

@@ Line 8: / Line 8: @@
 = Installation =
 Navigate to the file server on [http://hive.ee.uct.ac.za Hive] or go straight to the [https://www.xilinx.com/products/design-tools/vivado.html Vivado Download site], and scroll down to standalone installers. Grab the latest <strong>WebPack version</strong> of Vivado (See image). You may need to enter some details if using the Vivado site.
 [[File:Vivado-standalone.png|thumb]]
@@ Line 18: / Line 20: @@
 # Select where to install Vivado. Double check if you want to install for just the current user, or all users
 # If downloading, let it run. It will likely take a while
 = Installing Custom Board Definitions =

@@ Line 61: / Line 61: @@
 == Constraint Files ==
 Constraint files list constraints in the project, and also allow you to initialize and refer to pins in your HDL.
 You also need to ensure you set your constraint files as being for the target board. Right clock on the constraints file and select "Set as Target Constraint File".
-Take, for example, this snippet of the Nexys A7 constraints file:
+Below is a snippet of the Nexys A7 constraints file:
 <pre>

@@ Line 67: / Line 67: @@
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
-set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=SW[0]
+set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=SW[0]
-set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=SW[1]
+set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=SW[1]
 set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=LED[0]
@@ Line 74: / Line 74: @@
 </pre>
-This short constraints file enables the 100 MHz clock called "CLK100MHZ", and a two-bit "array" of switches called "sw" and LEDs called "LED". One could reference these in a Verilog module as follows:
+This short constraints file enables the 100 MHz clock called "CLK100MHZ", and a two-bit "array" of switches called "SW" and LEDs called "LED". One could reference these in a Verilog module as follows:
 <pre>
 module project_1(

@@ Line 67: / Line 67: @@
 create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100MHZ}];
-set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
+set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { sw[0] }]; #IO_L24N_T3_RS0_15 Sch=SW[0]
-set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
+set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { sw[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=SW[1]
-set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0]
+set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=LED[0]
-set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1]
+set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=LED[1]
 </pre>
@@ Line 78: / Line 78: @@
 module project_1(
      input	CLK100MHZ,
-     input[1:0] sw,
+     input[1:0] SW,
      output reg [1:0] LED
      );
@@ Line 84: / Line 84: @@
      always @(posedge CLK100MHZ) begin
-         LED[0] <= sw[0];
+         LED[0] <= SW[0];
-         LED[1] <= !sw[1];
+         LED[1] <= !SW[1];
      end