Difference between revisions of "Toolchains, Compilers And Makefiles"
(Created page with "== Toolchains == A toolchain is a collection of tools that, in this context enables you to write code for an embedded system. For C-based development, a toolchain may consist...") |
|||
| (4 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
| + | [[Category:Software]] | ||
== Toolchains == | == Toolchains == | ||
| Line 14: | Line 15: | ||
:A linker takes one or more object files and converts them into an executable which can run on the target system. | :A linker takes one or more object files and converts them into an executable which can run on the target system. | ||
| − | Usually the compiler, assembler and linker are all integrated into one single command which can be run. The most common of these is GCC (GNU | + | Usually the compiler, assembler and linker are all integrated into one single command which can be run. The most common of these is GCC (GNU Compiler Collection). |
| + | |||
| + | == Debugging == | ||
| + | Debugging is a very important aspect of development. For information on GDB, see [[GNU_Project_Debugger]]. | ||
== Compilation == | == Compilation == | ||
| Line 25: | Line 29: | ||
Make files are a way of simplifying the compilation and build process. | Make files are a way of simplifying the compilation and build process. | ||
| − | Here’s a | + | Here’s a simple example makefile: |
| − | < | + | <syntaxhighlight lang="make" line='line'>.RECIPEPREFIX += # Tells make that we are using spaces instead of tabs |
| − | CC = g++ | + | CC = g++ # CC sets the compiler we’re using |
CFLAGS = -lm -lrt # Set compiler flags | CFLAGS = -lm -lrt # Set compiler flags | ||
| Line 34: | Line 38: | ||
OBJS = obj/* # Directory containing object files | OBJS = obj/* # Directory containing object files | ||
| − | + | # Define the default rule, called when simply running "make" in terminal | |
| − | + | default: | |
| − | $(CC) $(INCLUDE) $(CFLAGS) -c src/Prac2.c -o obj/Prac2.o # Compile object files | + | $(CC) $(INCLUDE) $(CFLAGS) -c src/Prac2.c -o obj/Prac2.o # Compile object files |
$(CC) $(INCLUDE) $(CFLAGS) -c Tools/Timer.cpp -o obj/Timer.o # Compile library files | $(CC) $(INCLUDE) $(CFLAGS) -c Tools/Timer.cpp -o obj/Timer.o # Compile library files | ||
| − | $(CC) -o bin/Prac2 obj/Prac2.o obj/Timer.o $(CFLAGS) # Link object files into binary | + | $(CC) -o bin/Prac2 obj/Prac2.o obj/Timer.o $(CFLAGS) # Link object files into binary |
| − | + | # Define a new rule to be called when running "make run" in terminal | |
| + | run: | ||
bin/Prac2 # Run the Prac 2 binary | bin/Prac2 # Run the Prac 2 binary | ||
| − | + | # Define a new rule to be called when running "make clean" in terminal | |
| − | rm -rf $(PROG) $(OBJS) # Remove the compiled binaries and object files </ | + | clean: |
| + | rm -rf $(PROG) $(OBJS) # Remove the compiled binaries and object files | ||
| + | </syntaxhighlight> | ||
== Cross Compilation == | == Cross Compilation == | ||
Latest revision as of 11:22, 24 July 2020
Contents
Toolchains[edit]
A toolchain is a collection of tools that, in this context enables you to write code for an embedded system. For C-based development, a toolchain may consist of the following:
- A text editor or IDE
- This is used to write the code that you plan to run on your embedded system.
- Make
- An automation tool for compiling, linking, and executing files. More on this later.
- Compiler
- Turns the C code you’ve written into assembly
- Assembler
- Turns assembly code into binary object files
- Linker
- A linker takes one or more object files and converts them into an executable which can run on the target system.
Usually the compiler, assembler and linker are all integrated into one single command which can be run. The most common of these is GCC (GNU Compiler Collection).
Debugging[edit]
Debugging is a very important aspect of development. For information on GDB, see GNU_Project_Debugger.
Compilation[edit]
If you are on a Linux based system and you wish to compile something, you can run:
$ g++ <file>.c -o <compiled_file_name>
Make Files[edit]
https://www.gnu.org/software/make/manual/make.html
Make files are a way of simplifying the compilation and build process.
Here’s a simple example makefile:
1 .RECIPEPREFIX += # Tells make that we are using spaces instead of tabs
2 CC = g++ # CC sets the compiler we’re using
3 CFLAGS = -lm -lrt # Set compiler flags
4
5 PROG = bin/* # Directory containing binaries to run
6 OBJS = obj/* # Directory containing object files
7
8 # Define the default rule, called when simply running "make" in terminal
9 default:
10 $(CC) $(INCLUDE) $(CFLAGS) -c src/Prac2.c -o obj/Prac2.o # Compile object files
11 $(CC) $(INCLUDE) $(CFLAGS) -c Tools/Timer.cpp -o obj/Timer.o # Compile library files
12 $(CC) -o bin/Prac2 obj/Prac2.o obj/Timer.o $(CFLAGS) # Link object files into binary
13
14 # Define a new rule to be called when running "make run" in terminal
15 run:
16 bin/Prac2 # Run the Prac 2 binary
17
18 # Define a new rule to be called when running "make clean" in terminal
19 clean:
20 rm -rf $(PROG) $(OBJS) # Remove the compiled binaries and object files
Cross Compilation[edit]
When working with large programs for a system, or when writing programs for an embedded system, it may be useful to use a more powerful system such as a desktop machine to compile the program. This can save you time and effort.
JetBrains CLion[edit]
Thankfully, cross-compilation is a common task and companies know this, so they develop tools to make our lives easier (and make themselves money). In the interest of your education (and the hopes that you spend money on their tools at a later stage), they make these tools accessible to you. For instructions on how to install, configure and use CLion, see CLion.
