HDL Simulation

When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet timing constraints (timing simulation). This page covers some useful information on writing testbenches, as well simulators that are used in the department (and in some cases, instructions on how to use them). While there are of course many simulators, the ones below are used by academics, staff and researchers in the department.

Testbenches

Testbenches in HDL are modules that instantiate other modules.

Testbenches in Verilog

Testbenches in Verilog are simply modules that instantiate the DUT, control the inputs, and monitor the outputs accordingly. They usually contain a single DUT, an initial block to set starting conditions, and an always block to run the testbench. The general approach for a DUT is to use registers for inputs and wires for outputs. Of course there is much more to testbenches than that, but that is the short of it.

For example, take a module called ModuleToTest that is meant to display switch values on LEDs:

`timescale 1ns / 1ps  // Set time and precision

module testbench();

// Define our inputs and outputs
reg clk;
reg [3:0] switches;
wire [7:0] leds;

// Instantiate the device under test
ModuleToTest DUT(clk, switches, leds);

// Set initial conditions
initial 
begin
    clk <= 1;
    switches <= 0;
end

//toggle the clock
always begin
    #5 clk = ~clk;
end

endmodule

Verilog Testbench Directives

Verilog directives allow you to do things which are not usually possible in hardware, only through simulation. This includes printing data to a screen, loading data from a text file, or stopping the simulation.

For a quick reference list of commands, see this link.

Available Simulators

The following is a collection of some HDL simulators used in the department.

iVerilog

See this link for a tutorial on iVerilog.

Vivado

The Vivado Simulator comes as a part of the Vivado IDE. For details on the Vivado IDE, see Xilinx Vivado. For details specific to Vivado, you can find a video on simulation here.

Once you begin writing your modules you need to check that they’re working. You can do this through simulation.

Once you’ve synthesized your project, you should be able to click “Run simulation”.

This will only run a simulation of your top module. It is far more useful to create a testbench.

1. Right click "Simulation Sources" and Select "Add new"
   In the dialog box, ensure Simulation sources is selected.
2. Create it in a new simulation set, and use the checkbox to set it as active
   You can toggle which simulation source is active by setting it in the same way you'd set your top level module under design sources - just right click on the simulation source and select "Make active"
3. Create a file for your testbench
   It's a good idea to name it the same as the module you're testing, followed by a "_tb" to distinguish it. For example, if you're creating a test bench for a clock, you might call the file "clock_tb". This file will appear under "non module sources" in the simulation set until you add some code to it.
4. Add basic TB code to the modele
   A super simple testbench consists of a generated clock and an instantiation of the module you're testing. Add the simple clock generation code, save the file, and set it as top in the simulation source. See the example above.
5. You should now be able to instantiate modules and run behavioral simulations to ensure your design works. You can connect the modules in such a way to minic switches by setting register values and using delay constructs.