HDL Simulation

When creating HDL designs, simulation can be used to verify your logic (behavioral simulation) or ensure you meet timing constraints (timing simulation). This page covers simulators that are used in the department, and, in some cases, instructions on how to use them. While there are of course many simulators, the ones below are used by academics, staff and researchers in the department.

Vivado

The Vivado Simulator comes as a part of the Vivado IDE. For details on the Vivado IDE, see Xilinx Vivado. For details specific to Vivado, you can find a video on simulation here. Simulate your design to ensure it operates as expected. You can run test benches to fully test your code.

Once you begin writing your modules you’re going to check that they’re working. You can do this through simulation.

Once you’ve synthesized your project, you should be able to click “run simulation”.

This will only run a simulation of your top module. It is far more useful to create a testbench.

1. Right click "Simulation Sources" and Select "Add new"
   In the dialog box, ensure Simulation sources is selected.
2. Create it in a new simulation set, and use the checkbox to set it as active
   You can toggle which simulation source is active by setting it in the same way you'd set your top level module under design sources - just right click on the simulation source and select "Make active"
3. Create a file for your testbench
   It's a good idea to name it the same as the module you're testing, followed by a "_tb" to distinguish it. For example, if you're creating a test bench for a clock, you might call the file "clock_tb". This file will appear under "non module sources" in the simulation set until you add some code to it.
4. Add basic TB code to the modele
   A super simple testbench consists of a generated clock and an instantiation of the module you're testing. Add the simple clock generation code, save the file, and set it as top in the simulation source.

   module clock_tb();
   
   reg clk = 0; //create a fake clock signal
   
   //toggle the clock
   always begin
       #1 clk = ~clk;
   end
   
   endmodule
   

5. You should now be able to instantiate modules and run behavioral simulations to ensure your design works. You can connect the modules in such a way to minic switches by setting register values and using delay constructs.